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this is information on a product in full production. august 2012 doc id 12493 rev 6 1/18 18 stg4159 low-voltage 0.3 max. single spdt switch with break-before-make feature and 10 kv contact esd protection datasheet ? production data features wide operating voltage range: v cc (opr.) = 1.65 to 4.8 v low power dissipation: i cc = 0.2 a (max.) at t a = 85 c low on-resistance v in = 0 v: ?r on = 0.40 (max. t a = 25 c) at v cc = 2.25 v ?r on = 0.35 (max. t a = 25 c) at v cc = 3.0 v ?r on = 0.30 (max. t a = 25 c) at v cc = 4.3 v separate supply voltage for switch and control pin latch-up performance exceeds 100 ma per jesd 78, class ii esd performance tested on common channel (d pin) ? 10 kv iec-61000-4-2 esd, contact discharge ? 15 kv iec-61000-4-2 esd, air discharge esd performance test on all other pins ? 10 kv iec-61000-4-2 esd, contact discharge ? 500 v machine model (jesd22 a115-a) ? 1500 v charged-device model (jesd22 c101) description the stg4159 device is a high-speed cmos low- voltage single-analog spdt (single-pole dual- throw) switch or 2:1 multiplexer/demultiplexer switch fabricated in silicon gate c 2 mos technology. it is designed to operate from 1.65 to 4.8 v, making this device ideal for portable applications. it offers low on-resistance (0.30 ) at v cc = 4.3 v. the sel inputs are provided to control the switches. the switch s1 is on (connected to common port d) when the sel input is held high and off (high impedance state exists between the two ports) when sel is held low; the switch s2 is on (it is connected to common port d) when the sel input is held low and off (high impedance state exists between the two ports) when sel is held high. additional key features are fast switching speed, break-before-make delay time and ultra low-power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them esd immunity and transient excess voltage. flip chip 7 table 1. device summary order code package packaging STG4159BJR flip chip 7 tape and reel www.st.com
contents stg4159 2/18 doc id 12493 rev 6 contents 1 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
stg4159 logic diagram doc id 12493 rev 6 3/18 1 logic diagram figure 1. functional diagram figure 2. input equivalent circuit table 2. truth table sel switch s1 switch s2 honoff (1) loff (1) 1. high impedance. on sel s1 s2 d $n 3%, n3 n3 !-6
logic diagram stg4159 4/18 doc id 12493 rev 6 figure 3. pin connections table 3. pin assignment pin number symbol name and function 1 s1 independent channels 3 s2 independent channels 4v l logic supply voltage 5v cc positive supply voltage 6 sel control 7 d common channel 8 gnd ground (0 v) "um p view 4o p view 6 , 3 3%, 6 ## 3 3 $ 6 ## 3 $ '.$ 6 , 3%, '.$
stg4159 maximum rating doc id 12493 rev 6 5/18 2 maximum rating stressing the device above the rating listed in table 4: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 5: recommended operating conditions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4. absolute maximum ratings symbol parameter value unit v cc supply voltage -0.5 to 5.5 v v l logic supply voltage -0.5 to 5.5 v v i dc input voltage -0.5 to v cc + 0.5 v v ic dc control input voltage -0.5 to v l + 0.5 v v o dc output voltage -0.5 to v cc + 0.5 v i ikc dc input diode current on control pin (v sel < 0 v) -50 ma i ik dc input diode current (v sel < 0 v) 50 ma i ok dc output diode current 20 ma i o dc output current 300 ma i op dc output current peak (pulse at 1 ms, 10% duty cycle) 500 ma i cc or i gnd dc v cc or ground current 100 ma p d power dissipation at t a = 70 c (1) 1. derate above 70 c by 18.5 mw/c. 500 mw t stg storage temperature -65 to 150 c t l lead temperature (10 sec.) 260 c table 5. recommended operating conditions symbol parameter value unit v cc supply voltage 1.65 to 4.8 v v l logic supply voltage (1) 1. v l pin should not be left floating. 1.65 to v cc v v i input voltage 0 to v cc v v ic control input voltage 0 to v l v v o output voltage 0 to v cc v t op operating temperature -40 to 85 c dt/dv input rise and fall time control input v l = 1.65 to 2.7 v 0 to 20 ns/v v l = 3.0 to 4.8 v 0 to 10
electrical characteristics stg4159 6/18 doc id 12493 rev 6 3 electrical characteristics table 6. dc specifications symbol parameter test conditions value unit v cc (v) v l (v) t a = 25 c -40 to 85 c min. typ. max. min. max. v ih high level input voltage 1.65 - 4.3 1.65 - 1.95 1.25 ?? 1.25 ? v 2.3 - 2.7 1.75 ?? 1.75 ? 3.0 - 3.6 2.35 ?? 2.35 ? 4.3 2.8 ?? 2.8 ? v il low level input voltage 1.65 - 4.3 1.65 - 1.95 ?? 0.6 ? 0.6 v 2.3 - 2.7 ?? 0.8 ? 0.8 3.0 - 3.6 ?? 1.05 ? 1.05 4.3 ?? 1.5 ? 1.5 r on on-resistance 1.8 1.65 - 4.3 v s = 0 v to v cc i s = 100 ma ? 0.49 0.65 ? 0.85 2.25 ? 0.30 0.40 ? 0.50 3 ? 0.25 0.35 ? 0.45 3.7 ? 0.22 0.32 ? 0.42 4.3 ? 0.21 0.30 ? 0.40 r on on-resistance match between channels (1) 1.8 1.65 - 4.3 v s = 0 v to v cc i s = 100 ma ? 5 ??? m 2.25 ? 3 ??? 3 ? 3 ??? 3.7 ? 3 ??? 4.3 ? 3 ??? r flat on-resistance flatness (2) 1.8 1.65 - 4.3 v s = 0 v to v cc i s = 100 ma ? 300 400 ? 450 m 2.5 ? 130 170 ? 230 3 ? 90 120 ? 170 3.7 ? 90 120 ? 170 4.3 ? 90 120 ? 170 i off sn off state leakage current 1.65 - 4.3 1.65 - 4.3 v s = 0.3 to 4.0 v d = 0.3 to 4.0 -30 ? 30 -300 300 na
stg4159 electrical characteristics doc id 12493 rev 6 7/18 symbol parameter test conditions value unit v cc (v) v l (v) t a = 25 c -40 to 85 c min. typ. max. min. max. i on sn on state leakage current 1.65 - 4.3 1.65 - 4.3 v s = 0.3 to 4.0 v d = open -20 ? 20 -100 100 na i d d on state leakage current 1.65 - 4.3 1.65 - 4.3 v s = open v d = 0.3 to 4.0 -20 ? 20 -100 100 na i cc quiescent supply current 1.65 - 4.3 1.65 - 4.3 v sel =v cc or gnd -0.05 ? 0.05 -0.2 0.2 a i sel sel leakage current 1.65 - 4.3 1.65 - 4.3 v sel =4.3v or gnd -0.1 ? 0.1 -1 1 a 1. r on = r on(max) - r on(min). 2. flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. table 6. dc specifications (continued) table 7. ac electrical characteristics (c l = 35 pf, r l = 50 , t r = t f 5 ns) symbol parameter test conditions value unit v cc (v) v l (v) t a = 25 c -40 to 85 c min. typ. max. min. max. t plh , t phl propagation delay 1.65 - 1.95 1.65 - 4.3 ? 0.13 ??? ns 2.3 - 2.7 ? 0.15 ??? 3.0 - 3.3 ? 0.16 ??? 3.6 - 4.3 ? 0.16 ??? t on turn-on time 1.65 - 1.95 1.65 - 4.3 v s = v cc r l = 50 ? c l = 30 pf ? 95 123 ? 160 ns 2.3 - 2.7 ? 48 62 ? 80 3-3.6 ? 33 43 ? 56 4.3 ? 29 38 ? 49 t off turn-off time 1.65 - 1.95 1.65 - 4.3 v s = v cc r l = 50 ? c l = 30 pf ? 12 15 ? 20 ns 2.3 - 2.7 ? 12 16 ? 21 3-3.6 ? 13 17 ? 22 4.3 ? 13 17 ? 22 t d break-before- make time delay 1.65 - 1.95 1.65 - 4.3 c l = 35 pf r l = 50 ? v s = v cc /2 10 42 ??? ns 2.3 - 2.7 10 22 ??? 3 - 3.6 5 15 ??? 4.3 5 12 ???
electrical characteristics stg4159 8/18 doc id 12493 rev 6 symbol parameter test conditions value unit v cc (v) v l (v) t a = 25 c -40 to 85 c min. typ. max. min. max. q charge injection 1.65 - 1.95 1.65 - 4.3 c l = 1 nf v gen = 0 v ? 83 ??? pc 2.3 - 2.7 ? 98 ??? 3.0 - 3.3 ? 114 ??? 3.6 - 4.3 ? 140 ??? table 7. ac electrical characteristics (c l = 35 pf, r l = 50 , t r = t f 5 ns) (continued) table 8. analog switch characteristics (c l = 5 pf, r l = 50 , t a = 25 c) symbol parameter test conditions value unit v cc (v) v l (v) t a = 25 c -40 to 85 c min. typ. max. min. max. oirr off-isolation (1) 1.65 - 4.3 4.3 v s = 1 v rms f = 100 khz ? -69 ??? db xtalk crosstalk 1.65 - 4.3 4.3 v s = 1 v rms f = 100 khz ? -69 ??? db thd total harmonic distortion 2.3 - 4.3 4.3 r l = 600 ? c l = 50 pf v s = v cc v pp f = 600 hz to 20 khz ? 0.01 ??? % bw -3 db bandwidth (switch on) 1.65 - 4.3 4.3 r l = 50 ? ? 28 ??? mhz c sel control pin input capacitance 1.8 - 4.3 1.8 - 4.3 v l = v cc ? 30 ??? pf c sn sn port capacitance 1.8 - 4.3 1.8 - 4.3 v l = v cc ? 94 ??? c d d port capacitance when switch is enabled 1.8 - 4.3 1.8 - 4.3 v l = v cc ? 227 ??? 1. off-isolation = 20 log 10 (v d /v s ), v d = output, v s = input to off switch.
stg4159 test circuits doc id 12493 rev 6 9/18 4 test circuits figure 4. on-resistance figure 5. bandwidth figure 6. off leakage figure 7. channel-to-channel crosstalk figure 8. off-isolation am04072v1 am0407 3 v1 v am04074v1 am04075v1 am04076v1
test circuits stg4159 10/18 doc id 12493 rev 6 figure 9. test circuit 1. c l = 5/35 pf or equivalent: (includes jig capacitance). 2. r l = 50 or equivalent. 3. r t = z out of pulse generator (typically 50 ). figure 10. break-before-make time delay 1. v gen = 0 v, r gen = 0 , r l = 1 m , c l = 100 pf. figure 11. switching time and charge injection
stg4159 test circuits doc id 12493 rev 6 11/18 figure 12. turn-on, turn-off delay time
package information stg4159 12/18 doc id 12493 rev 6 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 13. flip chip 7 package outline 1. the terminal pin 1 on the bumps side is identified by a distinguishing feature (for instance by a circular ?clear area? - typically 0.1 mm diameter). the terminal pin 1 on the back-side of the product is identified by a distinguishing feature (for instance by a circular ?dot? - typically 0.5 mm diameter). 2. drawing not to scale.
stg4159 package information doc id 12493 rev 6 13/18 figure 14. footprint recommendations table 9. flip chip 7 package mechanical data symbol millimeters min. typ. max. a 0.585 0.65 0.715 a1 0.21 0.25 0.29 a2 ? 0.4 ? b 0.265 0.315 0.365 d 1.018 1.068 1.118 d1 ? 0.5 ? e 2.018 2.068 2.118 e1 ? 1.5 ? e 0.45 0.5 0.55 f ? 0.284 ? ccc ? 0.08 ? sd ? 0.25 ?
package information stg4159 14/18 doc id 12493 rev 6 figure 15. marking figure 16. flip chip 7 tape specification dot, st logo s1 = marking v = manufacturing location yww = datecode (y = year, ww = week)
stg4159 package information doc id 12493 rev 6 15/18 figure 17. flip chip 7 reel information (front view)
package information stg4159 16/18 doc id 12493 rev 6 figure 18. flip chip 7 reel information (rear view) .. . . .
stg4159 revision history doc id 12493 rev 6 17/18 6 revision history table 10. revision history date revision changes 05-may-2006 1 first release 22-nov-2006 2 schematic figure 1 on page 3 updated 17-apr-2007 3 typo in cover page description 06-may-2009 4 device summary table updated, watermark removed from all pages. 01-oct-2009 5 modified: figure 2 , figure 3 , section 4: test circuits and figure 13 . updated: t stg values in ta b l e 4 , removed footnote in tab le 5 . 30-aug-2012 6 updated section 2 (added cross-references), reformatted section 5 , added notes below figure 13 , updated table 9 (added ?sd? value, renumbered ta b l e 9 , removed footnote), renamed figure 17 and figure 18 , minor corrections throughout document.
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